OMEGA PHOTONICS SYSTEMS LLC — Department of Defense STTR Phase II: A20B-T004

Description

We propose to build a photonic matrix accelerator using coherent mixing and multi-dimensional detection to perform matrix multiplications for high-efficiency artificial neural network (ANN) processing. In particular, we focus on using analog photonic information processing to perform large-scale matrix multiplication, which is one of the most fundamental, yet most computationally intensive tasks, carried out in ANN. Though ANNs are predominantly trained and deployed with digital computers, biological neural networks are based solely on analog signal transmissions with randomness and low precision. However, the power efficiency of these networks is orders of magnitude higher than currently can be achieved with digital integrated circuits, suggesting the possibility of power efficient analog ANN accelerator implementations. The proposed matrix accelerator does not perform bit-level logical operations, but an analog computing device based on coherent detection is dedicated to accelerating the matrix-matrix multiplication with unprecedented scalability and low power dissipation. The results from Phase I suggests a clear path forward: an energy-efficient integrated photonic matrix accelerator (PMA) that can address computationally demanding ANN training and has great potential for wide adoption in computing clusters and datacenters. Based on the feasibility studies conducted, and the experiences we had, in Phase I photonic integrated circuit (PIC) design, we propose to accomplish the following tasks in Phase II, while focusing on expanding the scale and power efficiency of the PMA: Design and fabricate a PIC for 16×16 matrix-matrix multiplication PMA in one clock cycle. The modulators and photodiodes on the PIC will have an analog bandwidth of at least 25GHz, and the PMA will achieve a computing performance of 200 TOPS while consuming less than 10 W in power. Develop a peripheral electronic circuit for interfacing the PIC with general purpose processors. The electronic interface will include arrays of analog-to-digital converters (ADCs), and digital-to-analog converters (DACs), as well as FPGA units for real-time input compensation and signal processing. The electronic interface will achieve a matrix loading speed of at least 500MHz. Develop a fixed-point software interface with a PMA backend. The error-aware training methods developed in Phase I will be packaged as part of the fixed-point software library. Demonstrate the training and inferences of state-of-the-art ANN models on the PMA. Design the next-generation PMA. We look towards improving the level of parallelization, power efficiency, and speed. Our team is composed of researchers with extensive expertise in photonics devices, optical communication, and machine learning, and rich experience in technology transfer and commercialization.