Cerfe Labs, Inc. — Department of Energy STTR Phase I: 38d

Description

Quantum computing platforms use many dozens of metal wire to control the quantum bits or qubits, which are operating at milli-Kelvin temperatures. These metal wires connect to external electronics, which is used to control, and error correct the qubits as well as to communicate the results back from qubits. These connections usually originate at room-temperature and not only introduces huge amount of thermal noise but also hinders efficient scaling of quantum systems. A technological solution will be to bring the control electronics, which is purely classical, closer to the quantum circuits preferably in the same cryo-chamber as the quantum circuits. Eventually, classical electronics can be integrated on the same chip as the quantum circuits enabling heterogeneous integration and ultimate scaling of quantum systems. Without a cryogenic non-volatile memory (NVM) to locally store instructions for controlling, probing, and error correcting qubits, classical electronics will have to rely on metal connection to external memory. Brining memory into the cryostat system will also improve speed and provide real time control over the quantum circuits. In addition, a cryogenic NVM will also accelerate new features in quantum sensing, measurement, and communications applications that also work at low temperatures. Cerfe labs proposes a novel technology that can be the missing piece to enable scalable quantum systems. To directly address the problem of the cryogenic NVM, we believe that we have developed the first non-volatile cryogenic memory (CeRAM) based on orbital switching in strongly correlated electron materials. We have shown CeRAM operation down to 1.5 K, only limited by our testing setup. We believe that an analog memory like CeRAM can be as close to the qubits as possible, which can be utilized to reduce the number of external connections and thermal noise in the system, improve memory pipelining, and allow better control of qubits. Our phase I goal is to demonstrate, without doubt, that we have a cryogenic correlated electron switch compatible with quantum information science (QIS) goals. We will design and fabricate CeRAM devices with a variety of device sizes and materials in CMOS compatible environment. These devices will be tested below 1 K using specialized test equipment to account for device parasitic. We also plan to demonstrate pulsed switching ability of CeRAM that would be ideal for all quantum technologies. At the same time, we plan to engage closely with DoE and other system level performers of topic 38 to understand opportunities of integrating the cryogenic memory in various cryogenic quantum systems. For phase II and beyond, our aim is to integrate the cryogenic memory with logic control circuit and the quantum circuits on single chip for to ultimate scaling of quantum systems. While we maintain business goals in the commercial memory research markets, we believe a successful DoE QIS focused program fits well with our technology development path. It would allow us to mature our technology at the larger dimensions and lower bit counts required by QIS, and then we can proceed toward a much higher bit counts and device dimensions required by CMOS foundry technologies.