Katsman, Vladimir — National Aeronautics and Space Administration SBIR Phase I: S1

Description

Adsantec will develop a single package Application Specific Integrated Circuit, capable surviving and maintaining performance in high radiation environments (gt; 1 Mrad), including enhanced low dose rate sensitivity.nbsp; The DAC will have a sampling rate greater than 1 Gb/s with effective number of bits gt;6. The design will be based on the companyrsquo;s proprietary reconfigurable DAC architecture, which incorporates a patented pseudo straight forward synchronization algorithm (PSFS) and a patented rad hard clock recovery/Phase Lock Loop Scheme.The proposed PSFS will be implemented inside developed ASIC minimizing overhead during data transmission. In this design, ADSANTEC will employ proven SiGe bipolar transistor-based circuit blocks based on our hard-by-design methodology. The use of ADSANTECrsquo;s space qualified ASIC packaging will enable fabrication and test of a TRL 7 or higher ASIC prototype at the end of Phase II.