PARETO FRONTIER LLC — Department of Defense SBIR Phase I: N203-150

Description

Pareto Frontier proposes to accomplish the overall objective of achieving improvements in tactical network capacity and throughput via advanced digital processing techniques geared for implementation on the MIDS JTRS platform.  A substantial increase in spectral efficiency can be realized by minimizing the spacing between adjacent frequency hop channels. In order to realize these potential throughput gains the receiver must be able to tolerate the resulting adjacent channel interference (ACI) caused by partially overlapping channels.  While ACI mitigation is similar to generalized interference mitigation for Anti-Jam resilience, there are unique challenges and opportunities present which must be addressed properly to yield an optimal solution. To this end, Pareto Frontier proposes to enhance and extend its Omni-Spatial-Interference-Removal-Integrated-System (OSIRIS); a modular and scalable STAP engine that is able to fully exploit available degrees of freedom to provide maximum interference mitigation coverage under a wide range of environments.  The augmented solution will incorporate key elements specifically addressing mitigation of dynamic interference caused by neighboring channel pulses without impacting sensitivity or Anti-Jam capability of the baseline solution rendering the novel Adaptive Capacity Enhancing System With Interference Cancellation Leveraging Duality (ACES WILD), yielding a projected capacity gain of over 100% the baseline system. As part of the Phase 1 effort, Pareto Frontier will establish under the baseline task a comprehensive Matlab model of the solution and complete an FPGA processing architecture to facilitate projection of required FPGA resources. The solution will be further tailored to best fit within what is available on the MIDS platform hardware. Pareto Frontier will work extensively with its industry partner to ensure successful positioning for a Phase II transition and achievement of a TRL 6 demonstration. Transition preparation work will include detailed technical planning and design to properly embed the solution within relevant MIDS terminal hardware and logistical program planning to organize the work-flow involved in terminal design implementation, lab integration/test and final demonstration. Option activities will further mitigate hardware transition risk via completion of fixed-point algorithm conversion and proof-of-concept implementation on surrogate hardware along with extended MIDS integration risk mitigation.