The ReWall Company — National Aeronautics and Space Administration SBIR Phase I: Z2

Description

To address the needs of image processing and other data parallel scientific applications TCL proposesnbsp;RadRISCnbsp;a scalable architecture composed of simple cores based on the RISC-V ISA with a Single Instruction Multiple Data (SIMD) architecture similar in organization to modern GPU processors. The preliminary overall system architecture includes an array of RISC-V cores connected via a RapidIO fault tolerant switch which also enables connections to a fault tolerant external memory for program data and an independent fault tolerant memory for checkpointing. The RapidIO switch innbsp;RadRISCnbsp;also provides a connection to the hardware root of trust and any connected I/O devices or peripherals.nbsp;nbsp;An emphasis will be placed on keeping the cores relatively simple as this will enable more effective fault tolerance. The introduction of architectural complexity is an invitation to increase the potential failure points in a given processor design.nbsp;Whilenbsp;RadRISCnbsp;will have many robust reliability features it will not sacrifice performance. The targeted signal and image processing workloads will be highly data-parallel which drives a simple, in-order pipeline architecture fornbsp;RadRISCnbsp;in lieu of a complex out-of-order design to enable maximum performance-per-watt. Per-cycle performance will be further enhanced through the addition of a SIMD unit to take advantage of the data parallelism.nbsp;nbsp;Previous resilient processor architectures have focused on strictly protecting user code. However, thenbsp;RadRISCnbsp;hardware and software stack will protect code executed in machine mode, supervisor mode and user mode. This is enabled by the combination of the aforementioned hardware techniques as well as a series of compiler-driven software techniques. This compiler-centric approach allows us to subsequently compilenbsp;allnbsp;the software components required to operate the system. This system and software architecture can be modeled using Sandia National Laboratoriesrsquo; Structural Simulation Toolkit (SST).