ALPHACORE INC — National Aeronautics and Space Administration SBIR Phase I: S1

Description

According to the solicitation topic S1.03, NASA requires a low power, low mass, low volume, and low data rate RFI mitigating receiver back end that can be incorporated into existing and future radiometer designs. Alphacore proposes to design an application specific integrated circuit (ASIC) that provides significant SWAP (size, weight and power) reduction as compared to the existing board-level systems1 that use COTS ADCs and FPGAs with their total mass reaching kilograms. Alphacorersquo;s solution will be an ASIC that will have a 2 GS/S (gigasamples per second), 12-bit, lt;40mW, radiation hard ADC and a 256-channel back-end digital signal processing (DSP) block consuming lt;100mW.The ASIC will be developed in a small-geometry CMOS silicon on insulator (SOI) technology (28nm) that is inherently tolerant to relatively high total ionizing dose (at least 500krad(Si) can be expected), and has better immunity to single event effects than bulk CMOS processes (no latchup, better upset rate due to isolation). This system greatly benefits all future NASA missions that need systems to detect interference in different bands of frequencies. The results of this work also enable applications that require low-power receivers that incorporate ADCs and back-end filters, without the need for RFI mitigation. The proposed RFIM ASIC has much higher power efficiency along with expected better radiation hardness than the currently available solutions. The embedded ADC will also be offered as a separate intellectual property (IP) design block, and thus a stand-alone ADC can be fabricated as well. The impressive rad-hard ADC has, 30X lower power than the top-of-the-line space-qualified COTS ADC.7 Thus, the ADC itself is well-suited as an upgrade for numerous NASA missions.