CARBON TECHNOLOGY INC — Department of Energy SBIR Phase I: 06a

Description

Current microelectronic fabrication techniques have reached the end of Moore’s Law for miniaturization, and computing advances are limited by the physical limits of transistors and economic limitations of chip fabrication.1 Due to the strain of increased data demand on legacy systems, energy usage is at an all-time high and it is estimated that without advances in efficiency, the combined Information and Communications Technology (ICT) industries could consume 20% of all the world’s electricity by 2025, and be responsible for up to 5.5% of all carbon emission.2 Fabricating microelectronics using Atomic Precision (AP) can be an answer to advancing miniaturization and increasing electronic energy efficiency, but many challenges still remain in the development of manufacturing processes and materials for AP. Carbon Nanotubes (CNTs) have great potential for high performance electronic devices based on their superior transport properties, including high mobility, high current carrying capability, ballistic transport, and intrinsic linearity. Carbon Technology, Inc. (CTI) have made groundbreaking progress in the field of atomic precision manufacturing for Carbon Nanotube Based Field Effect Transistors (CNTFETs) through refinement of advanced techniques in Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Low Contact Resistance (via a proprietary “Clean Process”) and Doping for Schottky Barrier Control. The overall objective of this Phase I Project will be to continue refinement of the team’s accomplishments, by developing a CMOS compatible process for atomically pristine CNTFETs, further lowering Contact Resistance and demonstrating ALD protection of CNTFET based sensor arrays. The objectives above directly respond to the problem by advancing the development of AP microelectronics which will promote energy efficiency and allow for the continued miniaturization of electronics beyond that which is currently possible. Phase I will commence with high quality semiconducting enriched CNTs grown across 4” wafers with the goal of reaching CNT density of 10NT/um, with semiconducting to metallic NT ratio greater than 8 followed by integration of the new ALD recipe with the team’s proprietary “Clean Process” for Low Contact Resistance which will also help reduce hysteresis. Deposition of high quality dielectric films will also be attempted. Additionally, the team will refine their etching techniques for removal of the ALD layer which is required before the deposition of contact metal and for the channel area when used for sensor arrays. Finally, these new techniques will be measured to verify their success based on a number of different parameters. Inherently linear, CNTFETs are highly efficient, dissipating less unwanted power than current state of the art technology. This translates into higher data rates, improved capacity and more battery life for mobile and infrastructure systems. Linear amplifier transistors can serve both as Radio Frequency (RF) devices for transceivers and as on chip amplifiers for sensor arrays. The same benefit applies to RF transceivers which will link many of the anticipated billions of Internet of Things (IoT) devices. CNTFETs being developed by atomic precision will benefit the world by dramatically reducing all manners of physical and energy usage waste.