CARDINAL ENGINEERING, LLC — Department of Defense STTR Phase I: MDA19-T006

Description

State of the art power hardware-in-the-loop (PHIL) and controller hardware-in-the-loop (CHIL) methods and testbed are used to evaluate naval ship power architectures. An innovative approach is proposed to leverage these capabilities to generate an architecture and toolkit that provide near real-time digital emulated system-in-the-loop capabilities and code execution testing for missile defense systems. The development and testing of executable code software and firmware/hardware will be accelerated in an environment that is tailorable to represent any type of missile defense system. Accordingly, the environment will be capable of emulating embedded tactical processing architectures of mixed computing elements, as well as physical hardware and software running on physical processors-in-the-loop. This provides real-time hardware and tactical firmware V&V analysis and system integration capabilities for improved hardware, firmware, and software reliability, quality and maturity earlier in the development cycle than would otherwise be possible. Industries with complicated systems or advanced controls strategies face challenges associated with availability, cost, and maintenance of tactical hardware, software validation timelines, and system integration. These industries are adopting digital twin or emulation capabilities to test early in the design phase. The proposed environment is applicable to other industrial markets interested in developing and employing real time digital simulation/emulation capability. Approved for Public Release | 20-MDA-10398 (2 Mar 20)