DORNERWORKS, LTD. — National Aeronautics and Space Administration SBIR Phase I: Z6

DORNERWORKS, LTD. — SBIR Phase I award from National Aeronautics and Space Administration.

Amount
$124,846
Agency
National Aeronautics and Space Administration
Program / Phase
SBIR · Phase I
Topic
Z6
Solicitation
SBIR_19_P1
NAICS
Place of performance
MI
Period
2019-08-19 → 2020-02-18

Description

DornerWorks is seeking to enhance the capabilities and ecosystem of the open source Xen Project hypervisor, targeting full integration with the High Performance Space Computing (HPSC) platformrsquo;s High Performance Processing Subsystem (HPPS) through this project. There will be several tangible benefits stemming from this Phase I project.nbsp;This project will show the Xen Project hypervisor to be a viable, open source, bare metal, hypervisor solution for the HPSC. Embedded hypervisors have been ported to hardware similar to the HPSC-HPPS, like the Xilinx Zynq UltraScale+ MPSoC and the NXP i.MX 8, for products in several different commercial markets to:Help manage available processing power,Provide isolation between software components,Enable multiple operating systems running on the same processor, andMore easily support software redundancy.This project will also add capabilities and make improvements to the Xen Project hypervisor to better suit it for use with the HPSC hardware and software components. A gap analysis between the Xen Project hypervisorrsquo;s capabilities and HPSC requirements will have been performed, identifying remaining improvements or new feature to be implemented in Phase II. This project will also substantively improve the Xen ecosystem with regards to space programs and missions by adding Xen support of a real time operating system (RTOS), like RTEMS, on A53 processors. This will be of value to future programs targeting the HPSC, and of immediate value for programs currently developing software on similar hardware available today, such as the Xilinx MPSoC used on platforms like Innoflightrsquo;s CFC-400 Compact Hybrid Architecture for Multi-Parametric Sensing (CHAMPS) Flight Computer.