FREEDOM PHOTONICS LLC — Department of Energy STTR Phase II: 04a

Description

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM). The proposed work for Phase II (still ongoing) is to create an optical CPU-memory link utilizing both robust MZI based athermal bidirectional links (at 30Gbs) and also microring based denser WDM structures. The Phase II, specially the MZI based approach, enabled us to demonstrate record breaking optical links and set the stage for the commercialization stage. The exceptional high power and high temperature operation of the lasers developed by Freedom Photonics and the low loss coupling work performed by PLCC has made the planning for Phase IIb more straightforward. In this effort, we are proposing the commercialization of high-capacity short-reach (<2km) Silicon Photonic (SiPh) transceiver interconnects to address the challenges associated with next-generation high performance computing. Following the standardization of the 400GE, both 800GE and 1.6TE interconnects will be needed beyond 2020. Our 800GE SiPh transceiver optics will be socketed, therefore, pluggable onto main boards of servers, switches and router racks co-located with memory devices, switch ASICs, FPGAs, GPUs and CPUs to alleviate hyperscale data center power consumption and to support higher density, higher capacity optical links. The 800GE on-board optic (OBO) transceiver interconnect is expected to provide 100G per-lane and 200G per-lane electrical I/O interfaces with highest energy efficiency, lowest cost and higher bandwidth density compared to pluggable optics located on faceplates of server and switch racks. The Photonic Memory Controller developed have wide commercial applications in data center and telecom markets.