IERUS TECHNOLOGIES INC — Department of Defense SBIR Phase I: N202-095

Description

IERUS Technologies proposes to develop and demonstrate a methodology for evaluating synthetic aperture radar (SAR) and airborne electronic attack (AEA) hardware processing technology options. Technology and processing capabilities continue to change at a rapid pace. As the drivers for processing capability may change from gamers of a decade ago to today’s machine learning needs, there is a need for niche applications like radar processing to take advantage of these innovations. Whether or not radar processing may be unique to the current technology drivers, the longevity of the capability requires an ongoing evaluation of technology to measure its value for radar processing. Compounding the difficulty in comparing performance between hardware architectures is that the implementation of the algorithm must be tailored for each application. For example, GPU processing power measures in the TFLOPS, but this drops as the floating-point number precision increases; the complex valued, high dynamic range of SAR imagery requires precision that may result in performance less than advertised. While FPGAs have impressive resources, their processing capability depends precisely upon the particular chip, algorithm, access to memory, and design implementation.  For radar systems with low-volume of production of units, it is desirable to use COTS hardware to ride the wave of technological innovation and take advantage of cost savings of the marketplace. Non-recurring engineering costs (NRE) can be substantial to design, fabricate, integrate, and test a new processor every 12-18 months as new processing modules become available. General purpose workstation class computers are extremely cost-efficient in terms of raw processing power, memory, and data storage. However, these systems can be extremely large and power inefficient.  The focus of the phase 1 effort will be to develop a method to measure hardware processing performance specific to SAR, validate that method with a cost-effective and high-performance platform, and estimate processing hardware to scale the solution for a specific data throughput requirement.