INTELLISENSE SYSTEMS INC — Department of Defense SBIR Phase I: A20-099

Description

To address the Army’s need for secure Field Programable Gate Array (FPGA) zeroization for U.S. Military systems abandonment in foreign land, Intellisense Systems, Inc. proposes to develop a new Military Equipment Abandonment Solution for Programmable Assemblies (MEASPA). Specifically, the innovation in the FPGA zeroization strategy for programmable military assemblies will improve the security of programmable devices and prevent the risk of foreign entities being able to reverse engineer U.S. Military sensitive equipment. As a result, this technology offers a solution that can be implemented into legacy Line Replaceable Units (LRU), units under repair, and future LRUs, which directly addresses the Army requirements to secure FPGAs with a unique zeroization strategy. In Phase I, Intellisense will conduct a feasibility study through research on how current general-purpose FPGA boards and design logic can be adapted to the proposed design. We will analyze the MEASPA solution with simulations and hardware demonstration and evaluate the viability of the proposed zeroization solution for military, medical, and commercial applications. In Phase II, Intellisense plans to implement MEASPA’s logic design from a military ground vehicle on an FPGA platform (i.e., Altera or Xilinx) to show a proof-of-concept prototype, and create design logic for an FPGA using respective FPGA environments. This logic will implement a system’s design that meets military data encryption standards. Intellisense will also create software that can synthesize the FPGA logic with a zeroized design if given a command to do so. At the end of Phase II, Intellisense will have a working prototype of the MEASPA system. We will also have a business model ready for marketing the MEASPA system to commercial vendors.