MAXENTRIC TECHNOLOGIES LLC — Department of Defense SBIR Phase II: DMEA182-002

Description

To meet the demands of the DMEA182-002 SBIR solicitation (“Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property Protection”), the MaXentric and UCLA team proposes the HIGHFIVE (Heterogeneous Integration Guideline Highlighting Fabrication of Information Veiled Electronics), which provides a practical verification flow using the circuit-based model verification procedure. During Phase I, the team performed a trade-study on multiple chip-to-chip bonding process technologies. The team decided on one of candidates for UCLA’s Simple Universal Parallel intERface for CHIPS (SuperCHIPS) technology with the world finest pad pitch using the thermal compression bonding process. The team carefully selected figure-of-merit (FOM) circuits that were used to evaluate impact on the electrical performance when the manufacturing obfuscation technique is applied. During Phase I work, the UCLA and MaXentric characterized the chip-to-chip interconnect between the front-endof-line (active elements) and back-end-of-line (passive elements) layers, and simulate the performance of the FOM circuits for digital logic and analogy RF ASIC applications, respectively. During Phase II, the team will make a plan for fabrication and test of the FOM circuits, and develop a robust ecosystem for the interconnect.