Avalanche Technology, Inc. — National Aeronautics and Space Administration SBIR Phase I: H6
Avalanche Technology, Inc. — SBIR Phase I award from National Aeronautics and Space Administration.
- Amount
- $124,581
- Agency
- National Aeronautics and Space Administration
- Program / Phase
- SBIR · Phase I
- Topic
- H6
- Solicitation
- SBIR_19_P1
- NAICS
- —
- Place of performance
- CA
- Period
- 2019-08-19 → 2020-02-18
Description
Avalanche Technology will offer MRAM chiplets based on its pMTJ STT-MRAM technology. Avalanchersquo;s MRAM chiplets use Generic MRAM Interface (GMI). The GMI is modeled on the widely-used HBM interface and is optimized for memory accesses. In addition to the memory interface, MRAM chiplets need a second interface to communicate with the rest of the chiplets in a multi-chiplet system. For example, Intelrsquo;s Advanced Interface Bus (AIB) protocol is in the forefront for direct chiplet-to-chiplet communication for DARPArsquo;s CHIPS (Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies) program. To be used in AIB-based systems, Avalanchersquo;s MRAM chiplet will have an AIB interface and an adapter from the AIB to the HBM interface for the MRAM array.