CROSSFIELD TECHNOLOGY LLC — Department of Defense SBIR Phase I: N192-063

Description

Crossfield proposes a high dynamic range digitizer for Light Detection and Ranging (LIDAR). In order to achieve the performance, functional and size, weight, power, and cost (SWaP-C) objectives, the digitizer will use a state-of-the-art field programmable gate array (FPGA) system-on-chip (SoC) with integrated ultra-high-performance analog-to-digital converters (ADCs). The latest generation of the FPGA SoC incorporates up to eight 14-bit, 5 GSPS ADCs in the package, along with an ultra-low-jitter clock generator that supports precision synchronous sampling.The Xilinx Zynq Ultrascale+ FPGA RFSoC is a third-generation device optimized for high-performance RF frontends in radar and communications systems. The FPGA provides the resources (logic cells, flip-flops, LUTs) to support a variety of digital signal processing (DSP) algorithms to decimate the oversampled signals and compensate for DC offsets, gain mismatches and timing offsets.Using MATLAB/Simulink, Crossfield will explore combinations of oversampling, channel summing, channel stacking and parallel conversion techniques to achieve the performance objectives of 17 effective bits at 500 MSPS with a 50 MHz analog bandwidth.