INTELLIGENT COMPUTING MACHINES LLC — Department of Defense SBIR Phase I: SCO182-007

Description

We propose the analysis of a proposed architecture called ReMIX: Reconfigurable Machine Intelligence eXtreme compute architecture. This design is a chip multiprocessor with a non-von Neumann architecture and two layers of Network on Chip that enables low-power, high speed, parallel computations with very high throughput. Rather than have data traverse the memory hierarchy as is typical in von Neumann architectures, this work performs computations in memory to save energy. With a locally synchronous globally asynchronous architecture allowing for maximum flexibility depending on workloads, the individual processing blocks are coordinated by host processors that oversee the rest of the chip and coordinate the work being accomplished. Building on our previous experience with multiple pilot projects as well as most recently the DARPA UPSIDE project, in Phase I we will work on analyzing how to best allocate area on a proposed chip to get the most throughput and flexibility while minimizing power consumption for various applications including specifically high resolution, high frame rate computer vision applications.