EPIR, INC. — Department of Energy SBIR Phase II: C53-33b

Description

C53-33b-271095Recently developed precision timing detector technology based on silicon Low Gain Avalanche Diode (LGAD) although exhibiting excellent timing performance, cannot attain 10µm position resolution needed for advanced 4D detectors. New small-pitch detector solutions are being developed which necessitates development of complimentary Application Specific Integrated Circuits (ASICs) and reliable, high-density, low capacitance, readily manufacturable integration technologies to interconnect silicon pixel detectors with high density CMOS front-end integrated circuits. Overall objective of combined Phase I/Phase II project: Finalize design for the new custom multi-tier ASIC with Tier 1 – preamplifier, discriminator and charge injector, Tier 2 – Time-to-Digital converter and Tier 3 – readout circuitry while concurrently developing a versatile, high-density, high-yield, low-capacitance vertical integration approach based on modified direct bond interconnect technology (MoDiBI) to demonstrate vertically integrated multi-tier ASIC assembly. What was done in Phase I? Completed an optimized design for Tier 1 with simulated jitter of ~10ps. Developed a full detector array level thermo- mechanical model for 250µm-pitch ASIC based 3D integrated assembly complemented by experimental demonstration of LGAD-ETROC1 integration. The prototypes were tested successfully at Fermilab by electrical connectivity and charge injection tests for functionality. The Phase II effort is aimed at devising overall architecture of 250µm×250µm-pixel three-tier ASIC. Overall performance of the designed tiers will be validated by circuit SPICE simulation post-layout prior to tape-out to a foundry. Multi-tier integration technology will be demonstrated Through Silicon Vias (TSVs) and high-density, low- capacitance integration scheme employing patented Modified Direct Bond Interconnect technology supplemented by the 3D thermo-mechanical models for longer-term reliability. Large area hybridization techniques, die-to-wafer and wafer-to-wafer will be demonstrated for cost-effective solution. Fabricated individual ASIC tiers as well as final multi-tier assembly will be tested at Fermilab for operation by electrical connectivity and charge injection tests. Novel small-pixel, multi-tier ASIC integrated with high-density, low capacitance Modified Direct Bond Interconnect technology will find immediate application in detector chips to be used in newly conceived advanced Electron-Ion Collider (EIC) for precision timing and position application. Longer term applications include full vertically integrated highly segmented, high-density detectors for nuclear particle detectors, advanced infrared detector for defense and security application for active imaging systems, such as LAser Detection And Ranging (LADAR) and a wide variety of medical imaging applications such as Clinical dosimetry, Positron Emission Tomography (PET) to name a few.