WESTEST ENGINEERING CORP — Department of Defense SBIR Phase I: AF172-005
WESTEST ENGINEERING CORP — SBIR Phase I award from Department of Defense.
- Amount
- $145,736
- Agency
- Department of Defense · Air Force
- Program / Phase
- SBIR · Phase I
- Topic
- AF172-005
- Solicitation
- 2017.2
- NAICS
- —
- Place of performance
- UT
- Period
- 2017-12-05 → 2018-12-05
Description
Many custom and hybrid integrated circuits (ICs) and custom electronic components cannot bemodeled in simulation software because of their complexity and/or lack of technical data.TPS developers need to use a hardware modeler for these types of integrated circuits.The proposed WesTest Hardware Modeler will be compatible with LASAR and the VDATS Di-Series digital subsystem.It utilizes the Teradyne Di-series digital subsystem in conjunction with the Teradyne LASAR simulation software to model digital, hybrid and custom ICs and the circuit boards in which they are installed to produce fault dictionary and guided probe diagnostics for the VDATS Test Station.The hardware modeling system will have the ability to model multiple devices (both dynamic and static devices) simultaneously. It will be able to retain input (stimulus) and output patterns for entire clock cycles, and therefore, reestablish the state of the device under simulation in a repeatable manner.VDATS TPS developers and maintainers can benefit greatly from the WesTest Hardware Modeler by using the actual Teradyne Di-series digital hardware to perform the simulation. This type of simulation is performed on the actual test equipment used for the TPS so accurate simulation results are achieved.