ALPHACORE INC — Department of Energy SBIR Phase I: 27d

Description

While commercial, advanced optical transceivers can transmit data rates beyond 100Gb/s, they will not function in the high radiation environment present at the High Luminosity Large Hadron Collider (HL-LHC). These data transmission technologies are also too massive to be placed inside the HL-LHC detectors, where added mass degrades the measurements being made. The top custom-designed radiation-hardened optical transceivers that are available can work only up to the rate of 5.4Gb/s. This is in sharp contrast to the hundreds of terabytes of data per second that a single HL-LHC sub-detector needs to transmit. Thus, custom-designed, radiation-hard and size-optimized optical transceivers are required that can transmit data at rates up to 100Gb/s and beyond to meet the immediate HL-LHC need. Alphacore proposes to design 160 Gb/s radiation-hardened optical transceivers for the HL-LHC based on the advanced PAM-4 transceiver architecture. The data rate for a single driver in Alphacore’s unit transceiver will be 40Gb/s, 7.4 times higher than the existing fastest radiation-hard transceivers, which is a significant improvement and provides a possible solution to the HL-LHC data transmission problems. Alphacore’s unit transceivers can be combined to 160Gb/s or larger transceiver modules (200Gb/s). Alphacore will be teaming with the Unites States HL-LHC collaboration members in this R&D program. The circuits will be designed in the same process CERN is using to make most of the circuits for HL-LHC, and they will meet the total ionizing dose (TID) requirements of the HL-LHC inner trackers (1Grad(Si)). Alphacore has been following CERN’s TID test results for the proposed process and these results will be leveraged in this development. The ASIC will be also hardened against single event effects with techniques suggested in the recent CERN presentation on radiation effects and mitigation. The major circuits in this development include a 20GHz phased locked loop (PLL), a serializer and a laser driver that are all optimized for high data rate and extreme radiation hardness. The following tasks will be completed during the Phase I period: 1) Optimize the transceiver architecture, 2) Optimize the PLL architecture and complete its layout, 3) Optimize the current mode logic driver, 4) Design laser drivers, 5) Perform basic radiation effect simulations and apply RHBD techniques, 6) Integrate and complete the chip layout for the complete optical transceiver, and 7) Plan schedule and tasks for the Phase II program. The Phase I work will prepare the Alphacore team for prototype optimization, fabrication and evaluation which will occur during the Phase II program. Commercial Applications and Other Benefits: The completed product will have wide applicability to the different sub-detector systems at HL-LHC. In addition, this rad-hard optical transceiver is versatile and can be used in numerous other HEP experiments (such as the International Linear Collider) and in large Nuclear Physics experiments, such as the planned Electron-Ion Collider (EIC).