ALPHACORE INC — Department of Energy SBIR Phase II: 27j

Description

Several high energy physics experiments require accurate timing measurements and transient digitization at high sampling rates, equaling or exceeding 5 gigasamples per second (GSPS). To date, only a few transient digitizer chips have been developed for this purpose and they are based on storing the analog samples onto long buffers from which they are digitized with low-rate analog-to-digital converters (ADC). These digitizers provide low power dissipation per channel but they suffer from limited buffer length, long latency between samples (microseconds) and high jitter (> few picoseconds). A low-jitter continuously sampling ADC would be a solution to the problems described above, but the only available COTS ADCs in the > 5GSPS sampling rate range have way effective resolution that is too low (less than 8 bits) and power dissipation that is too high (> 4W) to be used in most experiments. The innovation is a low-power gigasample-range ADC that has both “continuous ADC” and “buffered waveform digitizer” functions. Continuous ADC mode: This mode is used when the input needs to be digitized for an extended period. There is no latency, no deadtime or buffer length limitations in this mode. The power dissipation is approximately 30mW per channel (for the 10b, 1.5GSPS prototype ADC), mostly consumed by the I/O circuits. The ADC provides seamless, high-speed interfacing to FPGAs (12.5Gb/s transceiver interface has already been evaluated on silicon, and we have lower data bandwidth options as well), which provides great benefits to system designers. Buffered waveform digitizer mode: In this mode 1,024 samples per channel are read into an on- chip digital memory buffer and can be read out at a lower rate (after a trigger, for example). The average power per channel is below 1mW (depending on the input pulse rate) per channel, since the data transmission bandwidth between the ASIC and an FPGA is low. The jitter and timing skew are both below 100fs and these values are in par with the reported numbers for state-of-the-art commercial gigasample-range ADCs. The timing measurement accuracy of the ADC is thus better than 1ps. The chip will be designed in a high-speed, low-power 28nm CMOS SOI technology that also provides inherent radiation hardness for total ionizing dose (inherently up to 200krad(Si) and up to 1Mrad(Si) with calibration) and single event effects (latchup eliminated, low SEU rate). If higher TID tolerance is