Jackson Labs Technologies, Inc. — Department of Defense SBIR Phase II: A17-051

Description

GPS Disciplined Oscillator (GPSDO) systems traditionally combine the 1PPS output from a GPS receiver and highly stable clock like a Chip Scale Atomic Clock (CSAC) to steer the local clock frequency to match the frequency and phase of the GPS-generated 1PPS. However, the GPS receiver does not take advantage of the stable Chip Scale Atomic Clock for improved GPS receiver resilience, improved position navigation and timing performance, and spoofing detection. This Phase II proposal shows how the disciplined oscillator clock can be used to improve GPS carrier and code tracking, mitigate multipath, jamming and spoofing and to detect GPS receiver and satellite system anomalies. With fixed position operation, using the CSAC oscillator as the GPS reference clock allows aiding the tracking loops, reducing the likelihood of tracking erroneous signals (i.e. benign interference or malicious spoofing). The same concept applies to mobile operation with a multi-sensor fusion of GPS receiver, CSAC oscillator and Inertial Navigation System (INS). The multi-sensor system can remove bad measurements and operate in INS / CSAC holdover during periods of jamming or detected spoofing. This Phase II proposal focuses on building a prototype single board system capable of implementing and testing/qualifying algorithms with tightly coupled GPS/CSAC/INS system.