INERTIALWAVE INC — National Aeronautics and Space Administration SBIR Phase I: S16

INERTIALWAVE INC — SBIR Phase I award from National Aeronautics and Space Administration.

Amount
$149,704
Agency
National Aeronautics and Space Administration
Program / Phase
SBIR · Phase I
Topic
S16
Solicitation
SBIR_23_P1
NAICS
Place of performance
CA
Period
2023-08-01 → 2024-02-02

Description

A Universal Resonator Controller (URC) ASIC is proposed, primarily to measure inertial sensors.nbsp; High performance, navigation-grade IMUs use discrete parts to sense accelerometers and gyroscopes.nbsp; By using ASICs instead of COTS ICs IMU size and power consumption can be reduced.nbsp; A major issue in both rad-hard and terrestrial IMU markets is the lack of volume for high-performance systems when spread out across many players.nbsp; It is not particularly feasible to develop a cutting-edge product with all the difficulties of an ASIC for a single specific sensor.nbsp; Instead, the URC casts a wide net, allowing integrators to pick and choose which sensors to interface with.nbsp; With only a handful of passives and support ICs, the proposed URC would be able to operate with most inertial sensors operating with resonant frequencies between 5kHz-150kHz.nbsp; Nearly any resonating system may be controlled or sensed with this architecture due to its flexible digital programmable settings and selected external passives.nbsp; A prototype with limited bandwidth and only amplitude modulation has been developed. nbsp;Both voltage and current transduction modes are already available.nbsp; Phase I efforts will be dedicated to improving and implementing targeted innovations.nbsp; Due to the duration of work and award amount Phase I focuses on simulation and selected transistor-level designs.nbsp; Radiation hardening methods will be simulated, ADC bandwidth improved, and frequency demodulation architectures designed.nbsp; The existing ADC will be migrated to a rad-hard process and architecturally improved to guard against SETs.nbsp; Phase II will then proceed with full chip design and migration efforts, culminating in the tapeout of a wide bandwidth, rad-hard URC ASIC with best in-class SWaP.