ALPHACORE INC — Department of Defense SBIR Phase II: MDA15-019

Description

Alphacore will develop and characterize a new digital readout integrated circuit (DROIC) with a novel capacitor counter-based in-pixel analog to digital converter (ADC) that uses significantly less layout area than a digital logic counter-based in-pixel ADC and thus allows fabricating the DROICs in reasonably priced 130nm and 180nm fabrication processes. Moving back from the 65nm node to 180nm node provides up to 90% cost savings, a welcome relief for the companies working in this field, which otherwise suffer from escalated fabrication costs. In addition to the lower costs, this architecture keeps the pixel area small, so that an area even below 15m x 15m is possible. In this novel approach, a 10b column ADC is used to read three 6-bit-to-9-bit-accurate analog values from three in-pixel capacitors and as combined, they form an 18-bit-to-27-bit-accurate readout value. The pixel readout is thus theoretically accurate enough for 27-bit dynamic range, although Alphacores goal is 23-bit dynamic range for the first prototype. Using an in-house, area-optimized, low-power 10b, 25MS/s, 5mW ADC intellectual property (IP) block as the column ADC, the stored analog values are read from three in-pixel capacitors. Approved for Public Release | 17-MDA-9219 (31 May 17)