QUICKFLEX INC. — Department of Defense SBIR Phase I: N152-096

Description

QuickFlex proposes the FlexDuo mission processing architecture to improve upon the cost and fault tolerance capabilities of current rotorcraft mission computers, while creating enhanced processing capabilities to empower the computationally intensive mission applications of the future. FlexDuo consists of a collection of FPGA-accelerated Processing Nodes with the capability to detect lost Processing Nodes and automatically restore their associated functionality. To accommodate various types of mission functions, FlexDuo provides a flexible execution model: functions may run on the CPU or be implemented on the FPGA for hardware acceleration. FlexDuo Processing Nodes are networked using AFDX, a widely deployed, high data-rate avionic network.<br>FlexDuo uses an ARINC 653 compliant RTOS to guarantee that functions will not interfere with each other when running on the CPU. In addition, FlexDuo uses an innovative technique to provide this kind of guarantee for functions placed on the FPGA. This gives FlexDuo FPGA-enhanced performance while preserving reliability and lowering certification hurdles. FlexDuo reduces cost by minimizing the use of aviation specific chips (which are costly due to lower production volumes), simplifying certification through function encapsulation, and providing a performance hedge against obsolescence.