TRIDENT SYSTEMS LLC — Department of Defense SBIR Phase II: N121-034

Description

In this work, Trident will develop an Ultra Digital RF Transceiver (UDRT) FPGA processor for high reliability applications. In Phase I of the SBIR, Trident demonstrated the feasibility of a high-speed, high fidelity, reprogrammable kernel for use in high-speed digitization and signal processing applications. Trident utilized FPGA processing hardware and implemented associated firmware and software to demonstrate that the processing requirements and key performance metrics could be met. Hardware was matured with higher rate digital conversion hardware and kernel re-configurability was implemented. Using internal research and development, Trident began the translation of the Virtex5 FPGA architecture to the Zynq UltraScale+ architecture and initiated prototyping activities that have demonstrated the technical feasibility of this approach. This Phase II SBIR effort proposes to complete the development of the skip generation processor based on Trident's Phase I developed architecture and existing Digital RF Transceiver. The resulting Phase II hardware will address the emerging need of the industry; significantly increasing processing power and flexibility, while balancing size, power and cost, in a highly reliable transceiver. This will push SDR technology to the point that numerous new transition paths are created for USG programs as well as other commercial applications.