HYPRES INC — Department of Defense SBIR Phase I: A16-035

Description

Low cost integrated transceiver solutions eliminating the bulk of analog preprocessing are extremely attractive for Satellite Communications (SATCOM), and other wideband RF applications. Building upon the digital-RF transmitter development using 32-nm silicon-on-insulator (SOI) CMOS, we propose to develop a digital-RF transceiver IC that will have an analog RF interface from 290 MHz to 3 GHz and a standard digital interface to commercial-off-the-shelf state-of-the-art FPGAs.In Phase I, we propose to investigate a time-interleaved hybrid pipelined-SAR receiver with an on-chip LC-tank phase locked loop, incorporating regenerative operational amplifiers, thermal noise cancellation and digital calibration techniques to achieve the solicited performance. The digital-RF transmit side performs the reverse operation of the receiver, collecting and combining signals from basebands to form a set of composite transmit signals that are intended to be transmitted over different RF bands. We also propose to extend the analog interface to higher frequencies using either an analog or a discrete-time continuous-amplitude mixer.