Mavric Semiconductor Inc — Department of Defense SBIR Phase I: ST15C-002

Description

This proposal outlines an FPAA-based analog processing architecture that supports multi-chip module cascading, can be integrated into complex mixed analog-digital processing environments and can host sophisticated signal processing algorithms such as PDE-derived algorithms. The central innovation of the proposed effort lies in the physical device approach to embedded computing that breaks the energy efficiency-barrier of traditional digital systems. We have also shown that power efficiency of digital systems is far worse than theoretical limits. We expect to achieve technical advances in the following areas: Refining the baseline system-level FPAA design for efficiently solving partial differential equations using analog signal processing. Demonstrating the generalizability of our design by implementing PDE solvers using bio-inspired circuits; and Demonstrating the scalability of our design implementing algorithms for big data analysis. Phase I will focus on the design and development of the analog processing architecture for efficient computation of partial differential equations; however, our extensive experience in developing and implementing sophisticated algorithms in analog hardware will allow an early investigation of three defense-relevant signal processing application: path planning; classification using HMM dendritic processing; and neuromorphic image processing.