Menara — Department of Defense SBIR Phase II: SB153-004

Description

High-performance, high-speed analog-to-digital converters (ADC) are becoming essential building blocks in many applications including wireless modems, optical communications, test equipment such as real-time oscilloscopes, and high-energy particle physics (e.g., CERN), to name a few. While several ADC architectures have been proposed, time-interleaved (TI) SAR (Successive Approximation Register) ADC, because of its low power and small silicon area, has become the de facto preferred design. Time-interleaving architecture is a promising way to improve the conversion rate in a given technology. It allows many channel ADCs to sample the incoming data sequentially while digitizing the input in parallel. Recent researches [1-3] in time-interleaved SAR ADC made impressive progress, pushing the conversion rate beyond 20GS/s with ENOB around 6b. The fastest time-interleaved SAR[5] to date reached 90GS/s, demonstrating that time-interleaved SAR is an optimum choice for high speed, medium resolution ADC. In this proposal, we describe in details the architecture, design, and simulations of a low-power, 8-bit TI-SAR ADC capable of operating at and above 64 GS/s, with better than 6b ENOB and an analog bandwidth of greater than30GHz.