Ocius Technologies LLC — Department of Defense SBIR Phase I: ST15C-002

Description

The objective is to design an analog (time-continuous) radiofrequency (RF) computation platform in the form of a software-defined RF integrated-circuit (IC) with supplementary digital logic for solving differential equation based simulations at speeds that are 1-2 orders of magnitude greater than available digital high-performance computation platforms. The maximum speed that the state-of-the-art digital systolic processors can operate is typically in the range of 2-3 GHz, whereas combination of modern RF micro-electro-mechanical systems (MEMS) and available deep sub-micro 32 nm RF complementary metal oxide semiconductor (CMOS) or Bi-polar CMOS mixed (BiCMOS) technology, which has a characteristic cut-off frequency (fT ) of 445GHz, can be used to fabricate high speed tunable analog computational processors that would lead to massive throughputs around 100 GHz. The proposed RF-IC analog computational platform solves a variety of highly-relevant MD linear and non-linear partial differential equations. The resulting product of this investigation is envisioned to be a device that will be a remarkable leap in the computation time for a solver of a general system of linear partial differential equations that allows wide applicability in many fields.