RINCON RESEARCH CORPORATION — Department of Defense SBIR Phase I: AF161-147

RINCON RESEARCH CORPORATION — SBIR Phase I award from Department of Defense.

Amount
$149,999
Agency
Department of Defense · Air Force
Program / Phase
SBIR · Phase I
Topic
AF161-147
Solicitation
2016.1
NAICS
Place of performance
AZ
Period
2016-09-15 → 2017-03-21

Description

ABSTRACT: The Air Force seeks a trade study into a GPS M-Code Acquisition engine that utilizes the M-Prime version of the M-Code signal to provide the ability to operate more effectively in contested environments where high levels of jamming of the GPS system are to be expected. RRC will leverage the considerable advances in silicon technology and improved insights into computational algorithms that have occurred since the inception of the GPS modernization program to design a highly jam-resistant GPS M-Code acquisition solution with rapid TTFF. RRC plans for direct acquisition of the M-Code signal without reliance on C/A-code or other less resilient waveforms. The proposed approach uses a frequency-domain algorithm with a cross ambiguity function (CAF) processor to efficiently implement high processing gain with a large search space in delay (ITU) and Doppler (IFU). RRCs proposed architecture achieves a very high level of dynamic range and both coherent and non-coherent processing gain to meet the performance specifications.; BENEFIT: In this study, we identify a full GPS receiver implementation and SDR-based architecture that provides low cost and flexibility to support custom and unique GPS receiver applications with benefits to a variety of customers in the Federal marketplace. The study bolsters RRCs ongoing commitment and investment in GPS technology, including current efforts to develop a software-defined GPS receiver using an embedded ARM processor on a Xilinx Zynq System-on-Chip (SoC). A portion of our effort in Phase II and Phase III is the development of an acquisition engine architecture that readily integrates with an SoC type architecture for the software-defined receiver. An important output of the study determines whether the acquisition engine is a standalone ASIC that operates as a co-processor or as an accelerator as part of a multi-chip solution, or if the acquisition engine is integrated as part of the SoC itself. This study represents an opportunity for RRC to commercialize a complete GPS receiver solution based on the critical technological advances developed under this SBIR.