SENSOR CREATIONS, INC. — Department of Energy SBIR Phase I: 30e

Description

Compared to existing accelerators modern High Energy Physics HEP) experiments impose several demanding conditions to new radiation detectors like higher particle rates, higher fluence and the need to cover much larger areas while at the same time providing improved position and timing resolution over a longer operation lifetime in a harsh radiation environment. Hybrid pixel detector arrays provide excellent tracking information in many of todays experiments, but their fabrication cost and the comparatively large amount of material from CMOS IC plus detector in the path of a minimum ionizing particle MIP) could be significantly improved upon with new technology for implementation in the next generation of HEP experiments. In order to solve this problem the idea is to develop a Monolithic Active Pixel Sensor MAPS), in a standard deep sub-micron CMOS technology, thereby leveraging the low cost high volume fabrication resources available through todays consumer application driven semiconductor industry. But although mobile phone type multi-megapixel camera chips are available at low cost, such an off-the-shelf product is not suited for MIP detection because: a) pixels are very small and have slow response times, b) sensors are processed with a handling wafer, increasing the amount of material in the beam path, c) charge collection is inefficient in low resistivity silicon due to the lack of an electric drift field, d) no noise reducing bandwidth limitation through shaping e) no pixel level signal discrimination for data and power reduction. We propose to develop a high resolution, monolithic, backside illuminated CMOS pixel array with a pitch of 50m or less on high-resistivity silicon, thinned to 50m. Phase I is divided into four main tasks: Conversion of SCIs existing deep depletion sensor camera into a detection system for minimum ionizing particles using the demonstrator chip developed as part of this phase I effort. Development of schematic and layout of MAPS demonstrator chip leveraging SCIs existing test chip. This chip will also be fabricated and tested during phase I. Layout, fabrication and hybridization of passive test array fabricated in our high rho CMOS technology onto established FE-I4 readout chip. Characterization of developed MAPS and hybrid array through our partnering research institution LBNL. At the end of phase I, the characteristics of a deep depletion monolithic silicon detector for MIP detection will have been measured and benchmarked relative to existing hybrid solutions. After successful completion of the propose phase I effort, the full size device will be developed with minimum risk in phase II. At the heart of the proposed project is the development of a low noise, high speed radiation detector with unprecedented spatial and temporal resolution. The technology developed in this program will enable novel image sensors for implementation in 3D day-/night vision cameras, highly sensitive low cost medical diagnostic instruments like DNA sequencers or advanced color sensors for inspection and monitoring of industrial fabrication processes.