Aegis Technologies Group, LLC, The — Department of Defense SBIR Phase II: The AEgis Technologies Group Inc. is proposing this Phase II SBIR development effort to ad

Description

The AEgis Technologies Group Inc. is proposing this Phase II SBIR development effort to address the data bandwidth bottleneck that currently exists between Hardware-in-the-loop (HWIL) Scene Generation computing clusters and the sensor stimulators. The existing data links use COTS based video interfaces that result in a bandwidth shortfall by at least 100x for applications in multispectral, hyperspectral, and laser radar. AEgis proposes a method of bypassing these COTS based interfaces using GPU-Direct and a custom parallel optical interface that meet and exceed the bandwidth requirements. Without this interface, it will be impossible to provide real-time, high-fidelity HWIL simulation required to adequately test these complex sensor/seeker systems. HWIL T & E allows systems to be exercised more rigorously at much less cost than can be achieved in flight testing. Thousands of scenarios can be run to test the sensor performance and the ability of the seeker algorithms to operate in real-world, non-idea operation. However, as the sensors/seekers improve, the requirements for test instruments become more challenging. Hyper-Computing clusters are being developed for phenomenology modeling needed to produce realistic stimuli. A new data communications bus is required to interface the clusters to stimulators and device under test. This proposal addresses that challenge.