EWA GOVERNMENT SYSTEMS, INC. — Department of Defense SBIR Phase I: EWA Government Systems Inc. (EWA GSI) along with University at Albany College of Nanoscale

Description

EWA Government Systems Inc. (EWA GSI) along with University at Albany College of Nanoscale Science and Engineering (CNSE) and the Rochester Institute of Technology (RIT), proposes to develop a low-power neuromorphic parallel processor (NPP). The Phase I technical objectives are: (1) design for one or more neuromorphic architecture(s) that will support the required NPP functionality, (2) develop the critical neuromorphic building blocks required for the proposed NPP architecture, (3) perform system design analysis to evaluate various building block and architecture configurations with a focus on implementation in the next generation hybrid CMOS semiconductor fabrication technology, and, (4) Draft the requirements specification that documents the NPP architecture, critical building blocks, functional requirements and performance characteristics. This Phase I effort will establish the preliminary NPP system design. In Phase II, we will implement the design and fabricate a tangible prototype NPP chipset, at the CNSE facilities. This SBIR initiative will lead to the development of innovative silicon-based NPP chipset designs that can transition to production.