HARMONIA HOLDINGS GROUP, LLC — Department of Defense SBIR Phase I: Central Processing Unit (CPU) chip makers made two advancements in recent years: (1) hyper

Description

Central Processing Unit (CPU) chip makers made two advancements in recent years: (1) hyper-threading (e.g., Intel HT technology) to allow a single processor core to execute multiple instructions simultaneously, and (2) fabrication of dies with multiple processor cores. Exploiting those requires new code in C#, Java, or other languages that embrace threads. A thread is a conventional sequential program, but threads can be scheduled to execute in parallel. A key challenge is that two threads must serialize their work on shared memory areas or data structures (or else one could destroy the data of the other thread), requiring special synchronization primitives (e.g., monitors, message passing). This is a non-trivial job for a programming team. Rise Multi-Core fills the need is for automated analysis that can improve older sequential code to make use of multiple cores. The Desired Future State is a tool to analyze existing legacy code and apply transformations it to effectively use threading and multi-cores to improve performance (e.g., lower time for route planning, or increased throughput for graphical operations).