HYPRES INC — Department of Defense STTR Phase I: HYPRES, in collaboration University of Massachusetts, proposes an energy-efficient hybrid-

Description

HYPRES, in collaboration University of Massachusetts, proposes an energy-efficient hybrid-temperature-heterogeneous-technology (HTHT) digital data link for interfacing 4K superconductor electronics with room-temperature electronics. Comprising several stages of cryogenic SiGe amplifiers at different temperatures, followed by equalization techniques, this data link will be designed to minimize the energy/bit figure-of-merit while exceeding the solicited specifications of 10^-12 bit-error rate (BER) at 30Gbps. Based on preliminary simulations, we believe that the design will extend to a 10^-15 BER at 50Gbps, and the power consumption per link will be 0.2mW on the 4K stage. Building on HYPRES"hybrid Josephson junction and transistor modeling infrastructure, we propose to complete the first set of IC designs in Phase I itself and release for fabrication. Upon testing these designs in Phase I option, we plan a second design iteration during the option period. This will be followed by a full implementation and demonstration with representative superconductor ICs and one of the ADR prototype systems in Phase II. During Phase I, we will also analyze the need for digital equalization, clock-data recovery and deserialization. We will also explore the design of an optical data link after SiGe amplifiers to get the data out of the cryostat without electromagnetic interference.