TOYON RESEARCH CORPORATION — Department of Defense SBIR Phase II: For more than a decade there has been interest in behavioral language entry and translatio

Description

For more than a decade there has been interest in behavioral language entry and translation to hardware description languages (HDL) for field programmable gate arrays (FPGAs). This has culminated in a wide array of electronic design automated (EDA) tools that can translate high level languages, such as C/C++ and their variants, to HDL. Largely driven by the EDA industry, these prior tools have been expensive, difficult to use, and generally requiring expert knowledge. As such, there has been, and continues to be, a wall between algorithms designers and code entry into FPGAs. Work in this proposed effort seeks to dramatically change this paradigm by focusing on FPGA entry based on industry-standard MATLAB. By combining this with Toyon supplied radio development platforms, supporting software, tutorials, and other documentation, we seek to provide a unified development environment for designing wireless communication systems. Furthermore, because the development flow is well integrated with other existing tools, such as Simulink HDL Coder and MATLAB C/C++ Coder, the approach is extensible and portable across different processor and FPGA families. Similarly, the approach is flexible in that any radio vendor can leverage the toolset in a general fashion.