RDRTEC INCORPORATED — Department of Defense SBIR Phase II: RDRTec Inc. and SAIC propose to develop and test innovative processor architectures for Ma

Description

RDRTec Inc. and SAIC propose to develop and test innovative processor architectures for Maritime Classification Aids (MCA) and Sense And Avoid (SAA) algorithms. MCA algorithms include ship classification and Automatic Target Recognition (ATR) for both stand-alone Inverse Synthetic Aperture Radar (ISAR) images and fusion with simultaneous EO/IR sensor images when available. SAA algorithms include radar signal processing, tracking, and avoidance in a multiple threat environment. Feature extraction, fusion and ATR algorithms are data intensive parallel signal processing applications. The commercial graphics and gaming industry are leading the way in a new class of general purpose graphics processors units (GPGPU). Many core processing architectures are now available for size, weight, power, and cost (SWaP-C) constrained DoD platforms. For data intensive parallel signal processing applications, computational performance improvements of 10x to 100x over current digital signal processing (DSP) implementations have proven achievable.