XCELERIUM INC — National Aeronautics and Space Administration SBIR Phase I: Z2

Description

Unlike GPUs, which are optimized for latency tolerant computations, DRSAP exploits memory locality systematically to achieve a power profile that is 50x lower than GP-GPUs.nbsp; Unlike conventional SIMD processors DRSAP dynamically reconfigures to support systolic dataflows for matrix and FFT computations, which allows it to achieve 20x speedup over SIMD and vector processors.nbsp; At the same time, DRSAP can offer ML computations for deep neural networks that is comparable to deep learning accelerators like NVDLA.nbsp;nbsp;DRSAP achieves these performance breakthroughs with dynamic reconfiguration. DRSAPrsquo;s internal datapath reconfigures 1 million times faster than FPGAs.nbsp; While FPGAs offer great flexibility to realize any hardware structure by reconfiguring LUTs, DRSAPrsquo;s reconfiguration is limited to computations and interconnections.nbsp; This allows DRSAP datapaths to execute at much faster clock rates and offer die-sizes that are more than 100x smaller for the same computations than leading FPGAs.nbsp;DRSAP is compliant with the RISC-V instruction set architecture (ISA), which provides a path for software portability, and access to a growing number of open-source tools and large and growing software ecosystem. nbsp;nbsp;Xceleriumrsquo;s DRSAP, combining convenience and flexibility of general-purpose processors with cost and power advantages of custom hardware, offers new degrees of freedom to meet NASA future energy efficient compute needs. Xcelerium proposes to establish the performance and energy benefits of DRSAP technology for space applications during Phase I and to develop plans for a space-grade prototype (to be completed in Phase II).