ALPHACORE INC — Department of Defense SBIR Phase I: N221-080

Description

Currently, non-deterministic Ethernet is utilized in many of the Navy's weapon and avionics systems, including hypersonics. This implementation has been found to lack guarantees on data delivery needed for safety-critical real-time control. There is a need to develop an event-driven, real-time deterministic Ethernet system that has the potential to accommodate the full spectrum of traffic criticality levels required in hard real-time applications such as hypersonic systems, as well as a variety of aerospace systems. Time-Triggered Ethernet (TTEthernet) Intellectual Property (IP) block is needed to unify real-time and non-deterministic traffic into a single coherent Ethernet-based communication network.   While Foreign-based TTEthernet implementations are already in use in some space applications, the U.S. Navy desires a U.S.-based implementation of trusted TTEthernet available in the form of an IP block, which is the goal of this SBIR program.  Moreover, Alphacore has communicated with Navy and it has been confirmed that not only the digital TTE IP block,  but also the associated physical layer (PHY) IP block (OSI Layer 1) are needed. It has also been confirmed that radiation hardening these IP blocks will be a great benefit to Navy.    This suits very well for Alphacore since we have extensive experience, not only in the digital IP domain, but also in the high-speed analog and mixed-signal harsh environments IP domain. The PHY layer IP block has many analog and mixed-signal components in it, such as an advanced SerDes. Radiation-hardened SerDes with data rate matching to this program is one of they key IP blocks in Alphacore’s portfolio. We also have on-going related funded IP development programs going on in all three CMOS processes that are the target processes of this development: Intel 22FFL (recently replaced with the Intel 16 process), the GlobalFoundries 12LP process and the Skywater 90RH fabrication process.