CERIUM LABORATORIES LLC — Department of Defense STTR Phase I: AFX20D-TCSO1

Description

Single Event Upsets (SEUs, also referred to as ‘bit flipping’) are unintended and unexpected changes to a computer’s memory. Such events have been blamed on in–flight termination of autopilot, automobiles being unable to stop accelerating, and incorrect fabrication of factory parts. The origin of SEUs can be in both software and hardware. This proposal will focus on hardware SEUs, which are often caused by cosmic ray showers. These high energy particles can switch the 0 or 1 state of a transistor. In the short term this manifests as a corruption of data. Repeated incidents cause microscopic ‘displacement damage’ which can render the device inoperable. The dominant particle causing SEUs at a given altitude is dependent on where a given particle species is created and how quickly it loses energy. Neutrons dominate radiation damage in the upper atmosphere. For memory chips which contain boron, a neutron can fission a 10B nucleus, creating two highly ionizing nuclei within the memory circuit. These two nuclei can rearrange charge (causing bit flips) and damage the atomic structure of the transistor. Cerium Labs has extensive experience in modifying memory chips to avoid neutron–induced SEUs. In this project we propose three phase approach to validate and ultimately create an 11B radiation hard memory chip supply chain. The three phases of our project are 1) measuring neutron induced SEUs aboard vital USAF systems, 2) re–manufacturing the relevant memory chips and confirming a lack of SEUs, and finally 3) submitting a report detailing suggested modifications to USAF vendor specifications and providing a supply chain for such radiation hard memory chips.