Silicon Space Technology Corporation — National Aeronautics and Space Administration SBIR Phase I: S3

Description

<p style="margin-left:0in; margin-right:0in">VORAGO Technologies will create a rad-hard I/O Expansion Chip for next generation spaceflight processor devices, including the High-Performance Spaceflight Computing (HPSC) Chiplet.</p><p style="margin-left:0in; margin-right:0in">&nbsp;</p><p style="margin-left:0in; margin-right:0in">The I/O Expansion chip will have multiple high-speed interfaces so that it can interface with a space processor and support high speed communications. It will also have programmable-voltage-level GPIO to support both non-differential communications protocols and general I/O expansion.</p><p style="margin-left:0in; margin-right:0in">&nbsp;</p><p style="margin-left:0in; margin-right:0in">The I/O expansion chip will provide dedicated hardware on the IC to support each of the communications protocols. The I/O expansion chip will also include an appropriate amount of memory and a multi-channel Direct Memory Access controller system to support simultaneous high-speed communications. To optimize power consumption, multiple PLL sources will be available on-chip to provide the appropriate clock generation for the on-chip communications controllers.</p><p style="margin-left:0in; margin-right:0in">&nbsp;</p><p style="margin-left:0in; margin-right:0in">An ARM&reg; A5 processor core will be included on the I/O Expansion Chip so that it can be used autonomously from the spaceflight processor device. This feature is expected to give the system designer good options for system level power saving modes as well as more system fault management capabilities.</p><p style="margin-left:0in; margin-right:0in">&nbsp;</p><p style="margin-left:0in; margin-right:0in">The I/O Expansion chip will be implemented using VORAGO Technologies proven radiation-hardening HARDSIL&reg; technology. HARDSIL technology will make the I/O Expansion chip immune from latch-up.</p>