PACIFIC MICROCHIP CORP. — National Aeronautics and Space Administration SBIR Phase I: S1.03

Description

Spectrometers currently employed or under development by NASA are based on a printed circuit board (PCB) including field programmable arrays (FPGAs) and a number of other discrete components. An application specific integrated circuit (ASIC) based spectrometer offers a great reduction in weight, volume and power consumption compared to the FPGA/PCB based implementation. This proposal aims to develop a radiation-hardened (RH) low-power (LP) poly-phase spectrometer (PPS) ASIC. The proposed RH LP PPS ASIC aims to achieve a 4GHz bandwidth and 214 (16384) frequency bins. In order to implement the required functionality and meet the specifications while consuming below 2.5W of power, the proposed ASIC will include a state-of-the-art ADC, a demultiplexer, a poly-phase filter bank, a windowing function, a fast-Fourier-transform core, a fast-Fourier-data analysis block, a data readout, a digital control unit and testing features. Tolerance to at least 4Mrads of total ionizing dose (TID) radiation and immunity to the single event effects (SEEs) will be achieved by employing radiation hardening by design, by layout, and by system techniques and also by applying an ultra-thin gate oxide technology for implementation. Low power consumption will be achieved by employing special multiplier-less-accumulators and multiplier-less-"butterflies". The power consumption will be further reduced by switching off the unused ASIC's blocks, down rating the clock frequency, eliminating unnecessary buffering and applying the 28nm CMOS technology. Phase I work will provide the proof of feasibility of implementing the proposed spectrometer ASIC. Phase II will result in the silicon proven ASIC's prototypes ready for commercialization in Phase III.