PACIFIC MICROCHIP CORP. — Department of Energy SBIR Phase II: C45-28a

Description

Pacific Microchip Corp. is developing an ASIC targeted for streaming (triggerless) readout of multichannel X-ray and gamma-ray detectors. The ASIC is digitizing and digitally processing signals from 32 detectors performing automatic triggering and event building by extracting the event related information (time of arrival, peak value, time of peak, time over threshold and channel address). Further, the data is wrapped into frames and shipped out through a high-speed serial interface. The ASIC employs a patent pending technology which makes possible high performance, low power consumption and high channel density that cannot be achieved in systems based on off-the-shelf components. The ASIC is expected to tolerate at least 10Mrad TID – an important feature for many detector systems. In Phase I, the ASIC’s architecture was developed and modeled, the critical circuits were designed, and the proof of feasibility was provided. Phase II resulted in the fabricated and tested ASIC’s prototype. In the proposed Phase IIB, we will fix all identified issues of the 1st prototype ASIC, produce a sufficient number of parts, test and characterize them, advertise the product, and start sales. To the best of our knowledge, there is no 32-channel ASIC targeted for detector streaming readout that combines high-speed digitization, digital pulse shaping, event detection, event building, and high-speed serial communications. Our ASIC will provide the functionality equivalent to what is currently realized using several ADC parts, an FPGA and a great number of wiring between the ADCs and the FPGA. By using a single part, our solution will offer a great reduction in volume, power consumption and cost. These parameters are extremely important in X-ray and gamma-ray imaging and spectroscopy instruments that require a large number of channels. In addition to NP and HEP instrumentation needs, the ASIC will satisfy the most demanding energy and timing measurement requirements in a variety of multichannel detectors being used for CT scanners, security screening, non-destructive testing, and lab instrumentation. The ASIC will be offered as a component and also as an IP block for integration on SoCs being developed by other companies.