PACIFIC MICROCHIP CORP. — Department of Defense SBIR Phase I: SB153-004

Description

Beam steering phased array antenna systems, 100Gb/s fiber optic receivers and a number of other systems under development by DoD and by the industry demand for ultrafast sampling ADCs to digitize the RF and broadband fiber optic signals for further processing in digital domain. Pacific Microchip Corp. proposes to design, produce and commercialize an 8-bit 56GS/s ADC which includes a novel background gain calibration system based on the calculation of the difference between squared output voltage of sub-ADCs in digital domain using 2 MSB outputs. The novel calibration will permit the ADC to maximize the SFDR and achieve SINAD ratio of at least 38dB while consuming below 500mW of power. The ADC is based on the time-interleaved SAR architecture with a capacitive DAC employing the split monotonic switching method as well as fractional reference voltage. During Phase I, we will design and verify the ADC architecture, the most critical circuits and the calibration block. During the projects Phase II, we will finish the design, fabricate, package using previously developed high-bandwidth chip carrier, test the proposed ADC and will make it ready for commercialization in Phase III.