Dsplogic Inc — Department of Defense SBIR Phase I: SB151-004

Description

This project seeks to overcome the barriers to leveraging advanced field programmable gate array (FPGA) devices, and to enable revolutionary new levels of productivity, robustness, and design optimization in FPGA-driven implementation. We focus on the broad domain of digital signal processing (DSP) applications, which encompasses many areas of great importance to the DoD, including Radar, Ladar, and electronic warfare. FPGAs are very attractive and often necessary computational resources in DSP systems. However, the increasing complexity and heterogeneity in modern FPGA platforms, combined with lengthy FPGA development cycles and limited application portability, contribute to relatively high life-cycle costs compared to modern embedded software systems. As a result, this important class of new computing devices is highly underutilized --- e.g., either the cost of development and validation is so high that such devices are not used, or due to lengthy design iterations using low-level, low productivity design abstractions, they are employed at performance levels that are significantly below their potential. Through a novel development of programming abstractions, model-based program analysis, and user-friendly tool support, this project aims to address the growing gap between the capabilities of modern FPGA devices, and those of conventional FPGA-based design methods involving low-level hardware description languages.