Dsplogic Inc — Department of Defense SBIR Phase I: Field Programmable Gate Arrays (FPGA) are a very attractive, and often necessary, computat

Dsplogic Inc — SBIR Phase I award from Department of Defense.

Amount
$148,250
Agency
Department of Defense · Navy
Program / Phase
SBIR · Phase I
Solicitation
2011.1
NAICS
Place of performance
MD
Period
2011-05-02

Description

Field Programmable Gate Arrays (FPGA) are a very attractive, and often necessary, computational resource for intensive Digital Signal Processing (DSP) applications, including guidance systems. Their balance of performance, power consumption, and size make them ideally suited to SWAP-constrained sensor, communication, and guidance applications. However, the lengthy FPGA development and validation cycle, combined with limited application portability, contribute to relatively high life-cycle costs compared to modern embedded software systems. We propose the development of a high-level graphical programming environment for FPGA-based DSP applications. This model-based design environment, based upon object-oriented hardware design principles, will facilitate rapid FPGA system design by algorithm engineers across multiple platforms. Support for rapid integration and re-use of Intellectual Property (IP) cores is central to the proposed effort.