A-TECH CORPORATION — Department of Defense SBIR Phase I: N132-145

Description

Pipelined radiation hardened analog-to-digital converters (ADC) typically provide 12-14 bit resolution conversion at >20 MSPS and have inherent multi-clock cycle latency. These converters use multiple sub-ranging stages and error correction circuitry and the high parts count results in large silicon footprints. ATA proposes designing an Advanced Radiation Hardened ADC (ARH-ADC) by implementing the innovative Residual Bit Extraction (RBE) architecture on a Rad-Hard by Design (RHBD) Via Configurable Array (VCA) Application Specific Integrated Circuit (ASIC). Our proposed architecture will provide 16 bit resolution at >25 MSPS with single clock cycle conversion and low parts count resulting in reduced silicon footprint. The targeted ASIC technology will provide a radiation-hardened by design part and the VCA ASIC development and fabrication costs are much lower than traditional ASIC costs. This approach will allow ATA to complete the design and simulation during the Phase I effort and prototype fabrication and test during the Phase II effort. Leveraging our existing RBE board level design further reduces development time and risk on this proposed Phase I effort.