SILICON TECHNOLOGIES, INC. — Department of Defense SBIR Phase I: ABSTRACT: Cache memory is normally built with Static Random-Access Memories (SRAM ) and a

SILICON TECHNOLOGIES, INC. — SBIR Phase I award from Department of Defense.

Amount
$150,000
Agency
Department of Defense · Air Force
Program / Phase
SBIR · Phase I
Solicitation
2014.1
NAICS
Place of performance
UT
Period
2014-06-20 → 2015-03-10

Description

ABSTRACT: Cache memory is normally built with Static Random-Access Memories (SRAM ) and are necessary for many applications, including sensors, hardware based radio station, wireless systems, instrumentation, video, and power. These applications are often used in harsh environments including the nuclear, space, and military markets. These radiation environments magnify the difficulty of designing complex SRAMs due to the fact that ionizing radiation and even a single ionizing particle can generate charge in the semiconductor circuit. The radiation can drastically alter the performance of the SRAM. For example, the effects of ionizing radiation on MOS transistors can cause SRAM cells to switch states. In addition, it can also cause shifts in the threshold voltage, changes in the gain and a marked increase in the leakage currents which significantly affect the periphery circuits. Silicon Technologies, Inc. propose to design and commercialize a high-density, high-performance, Rad Hard Cache RAM technology to serve space markets. We will review existing Cache RAM literature, evaluate findings, pick a process and technology to incorporate. Circuit design, layout and simulations will be included for a representative 64 MB SRAM with appropriate peripheral circuits. BENEFIT: The objective is to create a radiation hardened by design or by process 64MB Cache RAM circuit developed in a Trusted process and available to the Air Force and other DOD departments that require Cache RAM either as a standalone chip or as a IP block to be included in their Systems on a Chip. The Air Force will be able to reduce its NRE costs significantly on future SOC programs that require large SRAM solutions.