THE NAVSYS CORPORATION — Department of Defense SBIR Phase I: Under this SBIR NAVSYS proposes to develop a Tamper-Resistant Embedded Configurable Comput

Description

Under this SBIR NAVSYS proposes to develop a Tamper-Resistant Embedded Configurable Computer System (T-RECCS) suitable for use in small unmanned vehicles to handle their onboard processing requirements. The proposed architecture will utilize a combination of commercial off-the-shelf processing resources, including General Purpose Processors, Digital Signal Processors, Graphics Processor Units and Field Programmable Gate Arrays to serve as a basic computer building block for computation intensive embedded computing systems. The use of state of the art commercial components should result in significant power savings. We propose to implement an active tamper protection approach within this architecture that will protect sensitive information required for the mission from compromise should the unmanned vehicle be captured. Under the Phase I effort we shall develop the system architecture and identify suitable components for integration into the T-RECCS modular architecture. To demonstrate the feasibility of the proposed tamper resistant multiprocessor architecture, a model based design approach will be developed and benchmarks of sample applications needed to execute target detection and tracking, and guidance, navigation and control of the unmanned vehicles in support of their mission will be used to assess the processing resources needed for implementing a prototype system under the Phase II effort.