Silicon Space Technology Corporation — National Aeronautics and Space Administration SBIR Phase I: Z2

Description

This fault tolerant SoC architecture focuses on signal and data processing while offering anbsp;systematic way to improve mission communication and data processing capabilities, enhance computing performance and reduce memory requirements. This technology will allow for increased speed, energy efficiency and higher performance for computing in unknown and un-characterized space environments including the Moon and Mars and beyond.nbsp;We will mitigate against different types of radiation effects using proven circuit hardware and process-based techniques. These techniques include Triple-Mode Redundancy (TMR), Dual-Interlocked Cell (DICE) register elements and clock glitch filter circuit implementations as well as VORAGOrsquo;s HARDSILreg; process that prevents radiation-induced latch-up. For memories, we plan to implement Error Detection and Correction (EDAC) and scrubbing. We will evaluate and document the level of protection required by each rad-hard zone on the device, how to mitigate against radiation effects in each zone and calculate the expected radiation performance of each zone and the complete IC.nbsp;There are some obvious features of the SoC that we are quite certain will be included in the final device definition. These include the ARM Cortex M core, the ARM Ethos core, EDAC-protected SRAM (that is required to execute the software) and UART, I2C and SPI serial communications blocks. We may also include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) as well as a SpaceWire interface and a MIL-STD-1553B bus interface. Until the use-case analysis is complete, we will investigate what other industry-standard IP blocks to include on the final IC. These will likely include further communications modules to interface with common spacecraft bus systems and control-oriented IP blocks such as timers with Pulse Width Modulation (PWM) outputs. It is possible to include other IP blocks and peripherals to provide a full mixed-signal SoC.